A read only memory cell includes a single transistor. The transistor of the read only memory cell includes a drain, a gate, a source, a first conductor, a second conductor, and via. Further, a bit line is provided to a drain of a transistor, a word line is provided to the gate of the transistor and the source of the transistor is connected to the ground. The transistor of the read only memory cell is either programmed to logic zero or logic one.
FIG. 1 is a Prior Art illustrating a traditional read only memory cell 100 design. The Prior Art includes a drain 105, a source 110, and a poly layer 115. The read only memory cell 100 also includes a first conductor 120 connected to the drain 105, Further, the read only memory cell 100 includes another first conductor 130 connected to the source 110, Furthermore, the read only memory cell 100 includes a second conductor bit line 125, and a second conductor ground line 135. A connection can be established between the drain 105, the first conductor 120, the source 110, another first conductor 130, the second conductor 125 and another second conductor 135 in various ways depending on the programming of the read only memory cell 100 either to logic zero or logic one. The various ways of programming the read only memory cell 100 is done by using the contact areas A, B, C and D as shown in the Prior Art.
A method for programming logic zero on a read only memory cell 100 in the existing technique includes connecting the first conductor 120 to the second conductor 125 over a contact area A and connecting the first conductor 130 to the second conductor 135 over a contact area D. As another method of programming logic zero on a read only memory cell 100 includes connecting the first conductor 120 to second conductor 135 over a contact area B and connecting the first conductor 130 to second conductor 125 over a contact area C.
The method for programming logic one on a read only memory cell 100 includes connecting the first conductor 120 to a second conductor 125 over a contact area A and connecting the first conductor 130 to a second conductor 125 over a contact area C. As another method of programming logic one on a read only memory cell 100 includes connecting the first conductor 120 to a second conductor 135 over a contact area B and connecting the first conductor 130 to the second conductor 135 over a contact area D.
However, in the existing systems, the read only memory cell requires minimum area of first conductor to be present in the base read only memory cell. Both the first conductor 120 and the first conductor 130 have to adhere to the minimum area requirement of the design rules, hence limiting the size of read only memory cell.
In addition, in the existing read only memory cell, even though the second conductor 135 is a ground line and is electrically common between the two adjacent columns, it cannot be physically shared because the regions B and D can be unique for the two adjacent cells. This further limits the physical size of the read only memory cell.
In light of the foregoing discussion, there is a need of an efficient technique for manufacturing a compact read only memory cell.